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parallel architecture中文是什么意思

  • 并行結(jié)構(gòu)
  • 并行體系結(jié)構(gòu)

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  • 例句與用法
  • So the egress of digital processing system lies in the parallel architecture
    因而其信號處理機的出路在于體系結(jié)構(gòu)的并行化。
  • So the egress of digital processing systern lies in the parallel architecture
    因而其信號處理機的出路在于體系結(jié)構(gòu)的并行化。
  • At last , it describes the scalable parallel architecture of advanced wp system based on multiple sharcs
    最后分析了基于多sharc的vvp可擴展并行處理系統(tǒng)的組成方式和結(jié)構(gòu)特點。
  • The thesis analyses the key technology of computer parallel architecture by constructing a system for dual - computer system parallel processing
    本文通過構(gòu)建一個并行處理雙機系統(tǒng)分析了計算機并行系統(tǒng)的關(guān)鍵技術(shù)。
  • Theebe - cg algorithm does not require construction of the global matrix . it can be implemented efficiently on a massively parallel architecture
    Ebe - cg算法不需要構(gòu)造全局矩陣,它在大規(guī)模并行結(jié)構(gòu)中能被有效地實現(xiàn)。
  • The cg algorithm does not require construction of the global matrix . it can be implemented efficiently on a abstract massively parallel architecture
    共軛梯度算法不需要構(gòu)造全局矩陣,它在大規(guī)模并行結(jié)構(gòu)中能被有效地實現(xiàn)。
  • According to the structure of quasi - cyclic ldpc code , we can make a trade - off between hardware complexity and decoding throughput by applying semi - parallel architecture
    摘要利用準循環(huán)ldpc碼的結(jié)構(gòu)特點,使用半并行結(jié)構(gòu)的譯碼器可以實現(xiàn)復(fù)雜度和譯碼速率的有效折中。
  • Subsequently , a parallel architecture for the integer wavelet transform is present . and something about how the architecture works and some charts of this architecture are presented
    然后提出一種實現(xiàn)整數(shù)小波變換的并行結(jié)構(gòu),分析了該結(jié)構(gòu)內(nèi)部的工作流程,并給出了詳盡的原理圖。
  • The video server with parallel architecture can extend the area of video service system , because it can disperse users " requests and reduce the local load of server and local traffic of networks
    采用并行服務(wù)器體系結(jié)構(gòu)可以分散用戶請求、減輕服務(wù)器局部壓力和網(wǎng)絡(luò)局部流量,擴大視頻應(yīng)用的規(guī)模。
  • This paper , first , studies the parallel architecture of np , and describe the chief design method and parallel processing technology of np from hardware and software , which gives the profile of np ’ s parallel architecture
    本文首先研究了網(wǎng)絡(luò)處理器的并行體系結(jié)構(gòu)。從硬件和軟件兩個方面綜述了現(xiàn)代網(wǎng)絡(luò)處理器所使用的主要并行設(shè)計方法和并行處理模型。
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